The present invention generally relates to semiconductor devices and methods of producing semiconductor devices, and more particularly to a semiconductor device having a via hole for connecting multi-level interconnection and a method of producing such a semiconductor device.
FIG. 1A shows a plan view of a circuit pattern which is generated from component information of a via hole pattern by a computer aided design (CAD). FIG. 1B shows a cross sectional view of a semiconductor device which is produced based on the circuit pattern shown in FIG. 1A.
In FIG. 1A, a lattice grid pattern 1 is used as a basis for arranging circuit patterns on a screen of a CRT device. The position of each circuit pattern is determined by grids (intersections) 2 of the grid pattern 1. A via hole pattern 3 is used to connect an upper interconnection layer and a lower interconnection layer. Pad patterns 4 and 5 are respectively provided with respect to the upper and lower interconnection layers.
In order to guarantee a positive connection of the upper and lower interconnection layers via the via hole, the pad patterns 4 and 5 respectively are set larger than the region of the via hole pattern 3 by taking into account the alignment margin. In addition, when determining the pattern arrangement by the CAD, the pad patterns 4 and 5 are generated as component information of the via hole pattern 3 when the via hole pattern 3 is generated.
In FIG. 1B, a lower interconnection pad 7 made of Al is formed on a substrate 6. An upper interconnection pad 10 made of Al connects to the lower interconnection pad 7 via a via hole 9 which is formed in an interlayer insulator 8.
When the multi-level interconnection structure is formed using the conventional method of generating the circuit pattern, a stepped part is formed in an interlayer insulator 13 when a lower interconnection 12 is formed on a substrate 11 as shown in FIG. 2A. For this reason, an upper interconnection 15 which is made of Al may become thin at a part A or a dent B may be formed due to the stepped part.
Generally, when forming an Al layer on a stepped part, the Al flows to the lower part and the thickness of the Al layer at the stepped part becomes smaller than that at other parts. Particularly when a via hole exists near the stepped part, the thickness of the Al layer at the stepped part becomes extremely thin and a disconnection easily occurs. In addition, the dent in the Al layer at the via hole becomes deep, and it is extremely difficult to make a satisfactory 3-level or 4-level interconnection structure.
On the other hand, a lower interconnection 16 may be provided adjacent to the lower interconnection 12 as shown in FIG. 2B. In this case, a stepped part is formed in the interlayer insulator 13 in a vicinity of the via hole 14 on the side where no lower interconnection 16 is provided. As a result, when forming the via hole 14 by an exposure apparatus using a mask, the focal distance of the exposure apparatus becomes different depending on the location on the interlayer insulator 13, and it is impossible to accurately form the via hole 14. Consequently, the connection of the upper and lower interconnections 15 and 12 may become incomplete.
Furthermore, the upper interconnection 15 is sloped at a part C above the via hole 14. For this reason, it is difficult to use the part C as an interconnection pad when connecting the upper interconnection 15 to another upper interconnection (not shown) via a via hole (not shown), and a satisfactory multi-level interconnection having 3 or more levels is extremely difficult to realize.
FIG. 2C shows a case where an interconnection 17 is provided under the lower interconnection 12 via the interlayer insulator 13 and the interconnection 17 is adjacent to the lower interconnection 12 in the plan view. In this case, the lower interconnection 12 becomes sloped, and it is difficult to accurately form the via hole 14 above the sloped part of the lower interconnection 12. In addition, the upper interconnection 15 also becomes sloped above the via hole 14. Therefore, it is difficult to use the sloping part of the upper interconnection 15 as an interconnection pad when connecting the upper interconnection 15 to another upper interconnection (not shown) via a via hole (not shown), and a satisfactory multi-level interconnection having 3 or more levels is extremely difficult to realize.